The 40th edition of the


an IEEE event (since 1995)

Sinaia, Romania (11-14 October 2017)

Noise Variability-Aware Design of CMOS Integrated Circuits,
Matthias Bucher

The downscaling of CMOS technology, accompanied by the reduction of voltage headroom, has exacerbated the importance of variability. Low frequency noise (LFN) is known to be inversely related to device area. Variability of LFN and of random telegraph noise (RTN) are key limiting factors for the performance of many analog circuits. Circuits such as oscillators, SRAM, CMOS image sensors (CIS), etc. are ultimately limited by levels of noise and mismatch. Hence the understanding of the noise statistics, for its geometrical as well as bias-dependence, is essential. However, the variability of low frequency noise has generally not been well understood by designers, and has been addressed in process design kits (PDKs) only in rudimentary ways. 

The present paper first discusses the essential behavior of LFN statistics with bias and geometry. LFN variability is shown to be worst in weakly or moderately inverted MOS devices, and is furthermore deteriorated when the transistors are saturated. The essentials of a charge-based statistical LFN model including statistics, developed in the context of the charge-based EKV3 MOSFET model, will be shown to well cover measured data over bias and geometry. Finally, noise variability-aware design of an operational transconductance amplifier (OTA) is illustrated, using either worst-case or statistical simulation. This novel approach consitutes a new paradigm for full noise variability-aware CMOS design.