Project title: A novel technological approach towards High-Sensitivity temperature sensors based on SiC MOS capacitors
Acronim: HISens
Programme/ Project type: PNCDI IV - Program 5.2. Human Resources, Subprogram 5.2.1.Start in Research Research projects to stimulate young independent teams (TE 2023)
Contract no. 45TE⁄ 2025 (ID PN-IV-P2-2.1-TE-2023-1740)
Project Duration: 08/01/2025 - 31/12/2026
Project Budget: 500.000 lei
Contractor: National Institute of Research and Development in Microtechnologies – IMT Bucharest (www.imt.ro)
Contracting Authority: Executive Agency for Higher Education, Research, Development and Innovation Funding – UEFISCDI (www.uefiscdi.gov.ro)
Project manager: Dr. Răzvan PASCU (razvan.pascu@imt.ro)

The HiSens project aims to design and manufacture MOS capacitors with a new oxide growth technology, starting from a porous SiC substrate. The fabricated devices have applications in the field of wide-range temperature sensors, with increased sensitivity. The SiC substrate porosification process is based on two electrochemical etching techniques, assisted by UV light to accelerate the electron-hole pair generation process. A Si-rich surface is obtained due to the bonding of carbon atoms with oxygen in the etching solution, forming CO2, which is a volatile gas. Thus, the oxidation process becomes faster and can be obtained at temperatures lower than that of the initial SiC substrate. This grown oxide is to be improved by various techniques: post-oxidation annealing treatments in a controlled atmosphere, deposition of oxides with high dielectric constant or the use of a thin film of amorphous Si deposited on the porous surface of SiC before the oxidation process. The MOS device properties will be assessed through morpho-structural analyses and electrical characterizations obtained over a wide range of temperatures. By corroborating the results of the investigations, the effect of various physical and process parameters will be highlighted and will determine the performance of the temperature sensors, which leads to the completion of the fundamental objective of the project.

Project director: Razvan Pascu
Postdoctoral member: Pericle-Ion Varasteanu
Postdoctoral member: Gheorghe Pristavu
Postdoctoral member: Cosmin Romanitan
Phd student: Irina Bratosin
Phd student: Marius Stoian

The scope of the project: design and manufacture of MOS capacitors with a new oxide technology, starting from a porous SiC substrate

• Summary of the stage (December 2025)

  In this stage, the main objective of the HiSens project was to develop an innovative technology for obtaining porous silicon carbide (SiC) substrates starting from the commercial wafer. Subsequently, these will be used as a starting substrate for the manufacture of MOS capacitors with applications in the field of temperature sensors with high sensitivity, especially at cryogenic temperatures. Therefore, the focus of the stage was on obtaining a controlled porosification process, which improves the properties of the base material and significantly reduces the costs of the oxidation process, the critical step in the realization of a MOS device, especially when using a substrate with a large band gap, such as SiC. At the same time, the porofization process preliminary to the thermal oxidation process ensured an improved oxide/SiC interface due to the reduction of C atoms during the thermal process. These introduce a high density of traps at the oxide/SiC interface, reducing the performance of the MOS device as follows: mobility decreases (in the case of a MOS field effect transistor - MOSFET), higher leakage currents appear, increased instability at temperature variations, which would greatly affect the performance of the device when used as a temperature sensor.
  By porosifying the SiC substrate, the aim is to avoid the aggregation of C atoms at the oxide/SiC interface during the oxidation process, the MOS oxide layer resulting from a layer rich in silicon (Si) atoms. The technological process of porosification is based on the electrochemical corrosion of the SiC substrate, a process achieved through distinct techniques, assisted or not by illumination with UV radiation. The role of these illuminations is to accelerate the generation of electron-hole pairs, essential for the development of electrochemical reactions. Following the porosification process, the chemical composition of the surface changes, becoming richer in Si. The phenomenon occurs because the carbon atoms in the SiC structure react with the oxygen in the etching solution, forming carbon dioxide (CO₂) — a volatile gas that is eliminated, leaving behind a modified surface, optimal for the formation of the oxide used in the final structure of the MOS capacitor.
  In this stage, different porous SiC structures were obtained using recipes based on wet etching assisted or not from an electrical point of view. In addition, two lengths of a UV range were used to generate electron-hole generation, a phenomenon necessary for the mechanism of porofization of the SiC substrate.
  Starting from a porofized SiC substrate, a MOS oxide was thermally grown, in a vapor atmosphere, at a temperature of 1100°C, for 4h. In parallel, a control (non-porous SiC substrate) was oxidized under the same conditions, resulting in an oxide thickness of only 23-25 ​​nm, compared to the oxide resulting from the porous substrate, which has a thickness of over 700 nm. This result is remarkable, considering that to obtain such a thick thermally grown oxide on a non-porous SiC substrate requires a very long time, but also a higher temperature.
  To demonstrate the functionality of a MOS capacitor on SiC as a temperature sensor, in this stage conventional MOS capacitor structures were designed and fabricated starting from a non-porous SiC substrate. Different MOS capacitors on SiC were fabricated in terms of oxide obtaining. Therefore, the MOS oxide was thermally grown in a dry oxygen atmosphere, at a temperature of 1100°C. Two different oxidation techniques were used, namely:
  i) standard thermal oxidation of the SiC wafer for 2h, resulting in a MOS oxide thickness of approximately 14 nm: the MOS devices were named AO (as-oxidized);
  ii) MOS oxide obtained by a preliminary deposition of amorphous silicon, followed by oxidation at the same temperature of 1100°C, but in a time 4 times shorter (30 minutes). 3 different thicknesses of amorphous silicon were deposited (5, 10, and 15 nm, respectively), resulting in MOS oxide thicknesses of approximately: 14, 30, and 40 nm, respectively. The devices in these batches were named: a-Si 5, a-Si 10, and a-Si 15, respectively.
  The test devices were characterized electrically using capacitance-voltage characteristics obtained at different temperatures, demonstrating their functionality as temperature sensors. A shift towards positive voltages of the capacitance-voltage characteristics was observed with decreasing measurement temperature.