Cristian RAVARIU
An ultimate stage of the ultra-thin SOI-MOSFETs: the Nothing On Insulator Nanotransistors

Abstract.
The challenges in miniaturization push the “SOI” nanotechnologies to some ultimate manufacturing techniques: undulated Polysilicon sub-10 nm On Insulator, Silicon On Nothing MOSFET's or uni-atomic layer structures. Obviously, the SOI technologies become attractive in the nanodevices domain. The buried insulator is an excellent physical support in order to sustain those few atomic layers that carry out the nanodevice body. In this paper the starting point was a standard SOI-MOSFET, with 200 nm Si-film on 400 nm Oxide. The ID(VDS, VGS) curves were studied for thinner films: 10 nm, 1 nm, 0.3 nm and finally 0 nm. This paper presents as a last stage a Nothing On Insulator configuration, placed between two prominent Si-n⁺ regions. The effect of transistor is fulfilled via the substrate biasing that modulates the drain-source current. The NOI nanotransistor uses just the tunnel current between the source and drain n⁺-regions. It is a promising device for the miniaturised power devices.

Keywords: nanotransistors, modeling, simulations.